Freescale Semiconductor /MK53D10 /LCD /GCR

LCD duty select

0 (000): Use 1 BP (1/1 duty cycle).

1 (001): Use 2 BP (1/2 duty cycle).

2 (010): Use 3 BP (1/3 duty cycle).

3 (011): Use 4 BP (1/4 duty cycle). (Default)

4 (100): Use 5 BP (1/5 duty cycle).

5 (101): Use 6 BP (1/6 duty cycle).

6 (110): Use 7 BP (1/7 duty cycle).

7 (111): Use 8 BP (1/8 duty cycle).

LCD Clock Prescaler

LCD Clock Source Select

0 (0): Selects the default clock as the LCD clock source.

1 (1): Selects the alternate clock as the LCD clock source.

LCD Driver Enable

0 (0): All front plane and back plane pins are disabled. The LCD controller system is also disabled, and all LCD waveform generation clocks are stopped. V LL3 is connected to V DD internally.

1 (1): LCD controller driver system is enabled, and front plane and back plane waveforms are generated. All LCD pins, LCD_Pn, enabled using the LCD Pin Enable register, output an LCD driver waveform. The back plane pins output an LCD driver back plane waveform based on the settings of DUTY[2:0]. Charge pump or resistor bias is enabled.

LCD Stop

0 (0): Allows the LCD driver, charge pump, resistor bias network, and voltage regulator to continue running during Stop mode.

1 (1): Disables the LCD driver, charge pump, resistor bias network, and voltage regulator when MCU enters Stop mode.

LCD Wait

0 (0): Allows the LCD driver, charge pump, resistor bias network, and voltage regulator to continue running during Wait mode.

1 (1): Disables the LCD driver, charge pump, resistor bias network, and voltage regulator when MCU enters Wait mode.

LCD AlternateClock Divider

0 (0): Divide factor = 1 (No divide)

1 (1): Divide factor = 8

LCD Fault Detection Complete Interrupt Enable

0 (0): No interrupt request is generated by this event.

1 (1): When a fault is detected and FDCF bit is set, this event causes an interrupt request.

LCD Frame Frequency Interrupt Enable

0 (0): No interrupt request is generated by this event.

1 (1): When LCDIF bit is set, this event causes an interrupt request.

Voltage Supply Control

0 (00): Drive V LL2 internally from V DD .

1 (01): Drive V LL3 internally from V DD .

3 (11): Drive V LL3 externally from V DD or drive V LL1 internally from V IREG .

Load Adjust

High Reference Select

0 (0): Divide input, V IREG = 1.0 V for 3 V glass.

1 (1): Do not divide the input, V IREG = 1.67 V for 5 V glass.

Charge Pump or Resistor Bias Select

0 (0): LCD charge pump is disabled. Resistor network selected. (The internal 1/3-bias is forced.)

1 (1): LCD charge pump is selected. Resistor network disabled. (The internal 1/3-bias is forced.)

Regulated Voltage Trim

Regulated Voltage Enable

0 (0): Regulated voltage disabled.

1 (1): Regulated voltage enabled.